The present invention relates to clock signal generation. Particularly, this invention relates to clock signal generation with error-correction of input digital signals.
Digital video tape-recorders (VTRS) have a clock signal generator in the reproduction circuitry.
In clock signal generation, a signal reproduced from a storage medium is differentiated and transformed into a binary digital signal. The digital signal is compared in phase with a clock signal that has been generated. The difference between the comparison result and a reference voltage is used for controlling frequency oscillation to generate a clock signal. The generated clock signal is compared with the digital signal in a phase-lock loop circuitry.
The reference voltage is adjusted so that a oscillated frequency arrives at an average frequency of the digital signal.
The reference voltage, however, has been manually adjusted; and hence there is a demand for non-manually adjustable reference voltage regulation.
Moreover, such a manually-adjusted reference voltage will vary with time or temperature change to affect the performance of the phase-lock loop circuitry.
A purpose of the present invention is to provide an apparatus and a method of clock signal generation with no manual adjustments of a reference voltage supplied to a phase-lock loop circuitry, and almost no degradation of performance with time.
The present invention provides an apparatus for generating a clock signal including: a phase comparator to compare, in phase, an input digital signal with a clock signal that has already been generated; a differential amplifier to amplify the difference between the output of the phase comparator and a reference voltage; a first generator to generate a clock signal to be supplied to the phase comparator, based on the amplified difference; an accumulator to accumulate an amount of errors of the input digital signal; and a second generator to generate a reference voltage to be supplied to the differential amplifier within a range from a predetermined minimum voltage to a predetermined maximum voltage, a level of the generated reference voltage being adjusted according to the output of the accumulator, an operating point of the first generator being controlled by the level-adjusted reference voltage.
Moreover, the present invention provides a method of generating a clock signal. An input digital signal is compared in phase with a clock signal that has already been generated. The input digital signal is generated based on the clock signal. The difference between the comparison result and a reference voltage is amplified. A clock signal to be supplied for the comparison is generated based on the amplified difference. An amount of errors of the input digital signal is accumulated. The amount of errors depends on the comparison result in phase. A reference voltage to be supplied for the amplification is generated within a range from a predetermined minimum voltage to a predetermined minimum voltage. The level of the generated reference voltage is adjusted based on the accumulated errors. The operating point for the clock signal generation is controlled by the level-adjusted reference voltage.